1. Field of the Invention
The present invention relates generally to integrated circuit package technology and, more particularly, to an increased capacity semiconductor device or package which includes a leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe may extend externally from the package body or may be partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body.
Leadframes for semiconductor devices or packages can be largely classified into copper-based leadframes (copper/iron/phosphorous; 99.8/0.01/0.025), copper alloy-based leadframes (copper/chromium/tin/zinc; 99.0/0.25/0.22), and alloy 42-based leadframes (iron/nickel; 58.0/42.0) according to the composition of the elements or materials included in the leadframe. Exemplary semiconductor devices employing leadframes include a through-hole mounting dual type inline package (DIP), a surface mounting type quad flat package (QFP), and a small outline package (SOP). The aforementioned semiconductor devices are particularly advantageous for their smaller size and superior electrical performance.
Leadframe based semiconductor devices such as those described above are typically fabricated using techniques wherein material removal processes such as sawing or punching are used to effectively electrically isolate various leads of the individual leadframe within the semiconductor device from each other and further to separate multiple leadframes within a matrix-type array from each other. However, such sawing or punching process often results in undesirable burr formation on the individual leads of each semiconductor device. In those semiconductor devices wherein the pitch between the adjacent leads is small, such burrs could have the effect of electrically shorting certain leads to each other. To prevent this occurrence, post-treatment is necessarily performed to remove the burrs after completing the manufacturing process. However, the need to complete such post-treatment process increases the manufacturing cost, and may further degrade the reliability of the device. The present invention addresses this issue by providing a semiconductor device which includes a leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. These, as well as other features and attributes of the present invention will be discussed in more detail below.
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.